Logic Minimization Algorithms for VLSI Synthesis
A scholarly text on logic minimization methods for VLSI synthesis, covering algorithmic approaches and theory. Insight into how Boolean logic reductions impact circuit design. Customer insight: text mentions none
Highlights
- VLSI logic minimization focus
- theoretical algorithmic coverage
- multi-author perspectives
Pros
- focus on logic minimization for VLSI
- structured academic content
- authoritative contributors
Cons
- no featured insights in customer data
- highly specialized topic
- no price or availability details
